LAYRTON® manufactures only high performance drivers for led. Our product range comprises IP20 and IP65/66/67 versions, featuring double insulation between primary and secondary circuits (3750V) and from live to outer accessible parts (case). ´
Our designs are primarily intended for lighting applications such as outdoor, industrial, sport, residential, floodlighting, high-bays, tunnels etc.
Taking into consideration the highly demanding requirements existing for these kind of applications in values such as efficiency, ripple, power factor, protections, dimming, etc., there are two topologies mainly used for the design of the drivers for led.
The differentiation is based on the “DC converter” stage of the circuit.
Topology 1: Flyback converters. Mainly used for applications below 150W. They can be designed with two different topologies. The basic ones are single stage topologies and the more complex are the two stage converters which include a dedicated circuit for power factor correction.
Topology 2: LLC resonant converters. For all the range of power, specially from 150W.
In both cases we can also find:
As this brief does not expect to be a design guide but a general view on the electronic basis, we will focus on the power stages and their basic performance principles.
Figure 1 shows the basic schematic of a driver with a single stage Flyback converter:
Fig.1.- Basic schematic of driver with Flyback converter (1 stage).
It can be observed that the input to the converter (ViF) is a crude half-wave DC voltage. In this way, it can be used as a reference for the formation of the current wave (IP= IDS) so high-power factor is achieved.
A drawback of this circuit is that there will be a 100/120 Hz rather recognizable harmonic component and that it will pass on to the Vo output voltage.
On the other hand, in the two stage Flyback converter (fig. 2), the input signal (voltage) to the Flyback stage will be filtered through a DC link electrolytic capacitor. As a consequence, the 100/120Hz harmonic component passing on to the output will be of a very low level.
Fig.2.-General diagram of Driver with two stage Flyback configuration with graphics of voltages and currents.
The basis of the Flyback converter (assuming 2 stage version) is depicted in Figure 3 and could be summarized as follows:
Fig.3. DC/DC Flyback converter basis
The circuit mainly consists of a transformer and a MOSFET transistor connected in series with the primary inductance. The secondary has a rectifier diode connected in series. In parallel to the output a capacitor filters the rectified voltage to the load.
Basically, the transistor interrupts the current through the primary side inductance of the transformer, by means of a PWM square wave voltage signal applied to the gate in such a way that:
– With the transistor turned on (VDS= 0), the primary side current (IP= IDS) will increase linearly (and so the voltage through the inductance). The secondary does not supply any current to the load due to the reverse biased diode in series (see the convention of points where the induced voltage in the secondary has opposite sign to the primary voltage).
– When the transistor is turned off, the voltages in primary and secondary sides reverse (the primary inductance is no longer “load” and becomes “generator” to maintain the current flowing) and the forward biased diode let the current flow to the capacitor and the load. There must be a circuit to allow the primary inductance discharge its energy.
– Therefore, the longer the time the transistor is ON (closed), the higher the voltage level reached. Thus, the regulation of the output voltage will be controlled by changing that time. The lower the time, the higher the frequency and the output voltage will be reduced.
One of the main limitations of this type of converter is the behavior of the MOSFET transistor during the switching periods.
When switching the transistor to ON, its voltage is VDS= Vin with a superimposed voltage wave provoked by the resonance of the transistor parasitic capacitance and the transformer primary side inductance (Res2). This will cause losses, and a limitation of the allowable switching frequency.
Fig.4.- Vds voltage in the MOSFET. Resonances and ZVS.
This effect can be reduced through the identification of the minimum of the voltage waveform, and synchronizing the transistor turn on at that time. The circuit design (QR Flyback) must conform to the optimization of this procedure. The right-side diagram in fig. 4, shows the time where the transistor is turned on at the point where its voltage is closest to zero (first valley of the voltage wave).
Another drawback of this system is the fact that there is a voltage surge during the turn off due to another (Res1) resonance between the leakage inductance of the primary side and the parasitic transistor capacitance. Therefore, when the transistor turns off, its drain to source voltage will be the sum of:
– The input voltage, Vin. The worst case will be with highest value of supply voltage.
– The reflected output voltage.
– El voltage surge provoked in the primary inductance which is trying to cut abruptly a current flowing through an inductance. A snubber circuit will considerably reduce its value.
Resonant LLC converter
When it is necessary to obtain higher power density power supplies, switching losses in the transistor take on a key importance. The reason is that it is necessary to work at high frequencies in order to reduce the size of the passive components and so the losses.
To reduce the dominant switching losses and allow HF operation, the resonant LLC topology is recommended. It consists of two transistors (half-bridge version) that will generate a square wave voltage controlled by a PWM signal to their gates, and a resonant network formed with two inductances and a capacitor. One of these inductances will be realized using the magnetizing inductance of the transformer. These passive components involve higher conductive losses, but they will be compensated by the HF transistor switching efficiency.
Fig.5.- Simplified schematic of one driver with LLC resonant topology.
The key of the efficient performance of the LLC configuration is that the flowing current through the resonant tank is sinusoidal. Although a square wave voltage is applied to the circuit, the resonant network filters the higher harmonic contents.
This effect will allow a ZVS operation in the MOSFET,s (Zero Voltage Switching). Accordingly, the transistors will turn on at the time when their drain to source voltages are zero. This process is depicted in figure 6 below where the transition from Q1 ON to Q2 ON is detailed.
Fig.6.- Sinusoidal wave of current through the resonant tank and ZVS (Q1 turn off+deadtime+Q2 turn on).
After Q1 is turned off, and assuming the current through the resonant tank (assumed positive at that time, that is entering the resonant tank) will be maintained in an early stage (1) by the discharge of CP (parasitic capacitances of the circuit, mainly from the transistor). Once this capacitor is discharged, the anti-parallel diode DQ2 will be forward biased and will keep the current flowing, still entering the resonant tank (2). This is the time when the control will turn out the MOSFET Q2, as the drain to source voltage is that of the anti-parallel diode (neglectable) that will be then short circuited by the transistor (see IQ2).
As it has been explained before, before the anti-parallel diode is forward biased and the transistor is turned on, the drain to source voltage in the transistor is maintained by the parasitic capacitance. Consequently, it is necessary to wait for it to discharge completely before turning it on. It is achieved by inserting a controlled period of time called “deadtime” between the transition of Q1 to Q2 conduction.
It must be pointed out that this information is a brief on the standard performance and it may (it will) vary depending mainly on input voltages and load levels.
Rafael del Águila